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RF Design Environment - Wireless Test Benches |  |
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What is a Wireless Test Bench?A Wireless Test Bench (WTB) is a collection of preconfigured parameterized sources, measurements, and post-processing setups based on published specifications of a wireless standard packaged in an executable simulation flow. In RF Design Environment, Wireless Test Benches offer a seamless verification environment by combining all information that is relevant to RF verification from sources, circuit DUT, and measurements and standards-required setups and including an instrument link for bench verification. How Does WTB Help Designers?There is a major gap in the verification of highly integrated RF/Mixed signal products. This gap exists in all the stages of development flow, from concept to implementation. Traditional design tools do not provide a comprehensive verification methodology from concept to implementation. Wireless Test Benches have been designed with the recognition of the needs of real design houses and after extensive study of the roadblocks circuit and system designers face in their everyday work. The WTB addresses designers' needs in a number of ways:
Closing the Verification GapTraditional RF tests rely only on discrete-tone figures of merit such as 1-dB compression point, TOI, and group delay. These metrics are not adequate for design and verification of today's complex wireless standards. The RF designer needs to ensure that the design performs according to modulated measurements such as EVM, ACPR, and BER, as defined by a given standard. These standards generate waveforms with unique modulation and framing structures. The same standards require designs to be tested based on burst structure with pilot, idle, and active portions and with measurements specific to a portion of or on the composite waveform. Often these measurements require meeting specifications for different data rates and sometimes they need resolution at the bit level, requiring fully compliant parameterized sources and measurements. For example, a design may pass all the traditional performance figures of merit but fail a wireless standard requirement. Consider the 802.11a OFDM signal, in which data is modulated onto 52 separate subcarriers. The form of modulation applied to each subcarrier is changed depending on the data rate being used. In order to transmit the highest supported rate of 54 Mbits/s, 64 QAM modulation is applied to each subcarrier. To ensure good linearity performance over all subcarriers, an average EVM measurement is made using an appropriate test system such as Agilent 89600 VSA. The maximum allowed EVM at the 54Mbits/s rate is 5.6%. The WLAN test bench offers this capability in the form of a fully parameterized source, 89600 VSA instrument-compatible measurement, and all the required setups based on standard specifications. The circuit designer's job is to verify his or her design on this test bench. The following two illustrations show: the test bench user interface and the parameters relevant to EVM measurement for WLAN; and the detailed simulation results for EVM that were obtained in a typical case.
Instrument ConnectivityThe wireless test benches take the verification challenge one step further by providing connectivity to Agilent instruments.
In the test bench user interface, notice the tab Signal to ESG. This is for selecting download into an ESG signal generator. The user can download the output of the DUT and verify the simulation results with actual bench measurements. Through this instrument connectivity, the circuit designer can compare the virtual verification with early prototype hardware of the design on the bench, or utilize measured data on the bench for generating more realistic models for simulation. Handshake Between System and Circuit DesignEstablishing a natural flow between system and circuit design is a daunting task. The designs are constantly being tuned, supplemented and optimized at system and circuit levels. Therefore, system and circuit designers need to communicate these changes in a channel tightly integrated with their home-based tool. The WTB flow depicted in the figure below shows the process where this handshake happens. System designer space (ADS Ptolemy) is shown on the left where the tasks of design partitioning and optimization of baseband and RF design is performed. Circuit design space is shown on the right. This is the RFDE ADE environment where new RFIC circuits are designed, fine-tuned and optimized using ADSsim. The WTB space in the middle can be thought as an exchange medium where preconfigured test benches as well as custom benches reside and shared.
Early Circuit DesignPrior to handshake, the system designer is busy working on his top-level design in Agilent Ptolemy while the RF circuit designer is using RFDE environment for circuit design. For this early work, the circuit designer has access to a collection of place-able sources and expressions available at circuit schematic. While WTB are designed for verification of transmitter and receivers especially through BER test bench, wireless sources and measurement expressions are intended for transmitter testing and therefore only parameters relevant for transmitter testing are included in the wireless sources. The illustration below shows a circuit design with a WLAN source and the spectrum, WLAN burst and EVM at two different nodes in the design.
WTB: Under-the-Hood ViewWireless Test Benches integrate the best from many domains: DSP/baseband simulation with Analog/RF in the Cadence flow. The overall block level representation of a WTB for both transmitter and receiver scenarios includes sources and measurements at RF and DSP levels. The overall configuration of a WTB is shown below.
The WTB interface, shown below, allows a WTB for a given technology to be connected to the circuit DUT that is going to be verified. WTB (left) and DUT (right) representation are highlighted. This illustration also shows what the WTB and DUT represent. At the top of the figure the simulation technologies and below figure the schematic used are shown.
Once the bench is connected to the DUT, the next steps are to provide the source, measurement and analysis (simulation) parameters that are relevant to a particular scenario and initiate simulation. The RFIC circuit design (DUT) is simulated with ADS Circuit Envelope while the bench (Source and Measurement) is simulated with the Agilent Ptolemy engine. Circuit envelope analysis is complemented with Automatic Verification Modeling (AVM) or Fast Cosim to make simulation of large and complex circuits a reality. Speed-ups of 100x and more have been verified using this simulation technology. Preconfigured Test BenchesBecause wireless standards require specific tests, the new release includes an extensive set of pre-configured test benches. The preconfigured test benches in are for WLAN, TDSCDMA and 3GPP formats. In addition, new test benches can be generated and exported from ADS making them available to circuit designers to test and verify their designs. The following illustration shows the preconfigured test benches that are offered in RFDE.
Transmitter and Receiver ExamplesThe following section introduces a transmitter and a receiver example. TDSCDMA Downlink Multicarrier TransmitterTDSCDMA downlink multicarrier is one of the transmitter tests according to 3GPP Standard R4 specification. The DUT used in simulation is a transistor level model of Agilent MGA 545P8 used as a pre-amplifier. The MGA-545P8 has a broadband P1dB across 1-6GHz, and can be used also as a driver amplifier. One of the measurements included in this test bench is CCDF (Complementary Cumulative Distribution Function). The TD-SCDMA signal model used in the test bench is compatible with Agilent Signal Studio software for transmitter test. Simulated CCDF curves for 1, 2 and 3 multicarrier scenarios are shown below. Note the detailed simulation results, which include the mean, peak and average power at the input and output of MGA-545P8 as well as number of carriers, number of channels and the CCDF as part of preconfigured setup. Similar setups exist for envelope, constellation, spectrum, EVM and BER.
WLAN Adjacent Channel Receiver SensitivityThe process of testing a given LNA circuit for BER/PER compliance using WLAN WTB is described here. In this experiment we again used the Agilent MGA 545P8 to measure WLAN PER and BER. The MGA-545P8 is a leading-edge 0.5-micron gate length GaAs Enhancement-mode pHEMT technology and its low power and small size satisfy the demand for compact 5 to 6GHz wireless LAN applications. In particular we were interested in the BER/PER values as a function of adjacent channel power. Once the amplifier circuit design was ready, the following steps were taken using the preconfigured setups:
The simulation took less than 10 minutes per BER/PER points on an HP workstation. The (circuit) size of problem (i.e., number of Harmonic Balance equations) was 483. The illustration below depicts the BER and PER results as a function of adjacent channel power. Using these curves, and the requirements of WLAN signal, one is more confident of the system level performance of the circuit design. This process can be repeated as the design size grows with the addition of other modules.
ConclusionToday's RF/Analog/Mixed Signal IC single-chip transceiver designers need both time and frequency domain simulators in one environment. We have seen above that in order to perform a full design and analysis, frequency-domain simulation is vital. It complements the time-domain simulation to extract the needed design information. RFDE provides these frequency-based simulators from within the Cadence design environment. |
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