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Agilent's GoldenGate is the leading RFIC Simulator platform delivering high capacity and unique analysis for full chip verification and design for yield. Developed for the specific needs of RFIC/Wireless designers, GoldenGate is fully integrated into the Cadence Analog Design Environment (ADE).
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Click on the following links for more information.
Upcoming Training Event!
RFIC Design Seminar: Increasing Simulation Coverage -- Offered at 5 locations will be a half-day seminar providing solutions to key design issues for Wireless / RFIC designers using Agilent EEsof's GoldenGate RFIC Simulator. Visit the Events page for more details.
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GoldenGate's Value
GoldenGate's unique algorithms are optimized for the challenging demands of modern complex radio design. These demands require a simulator with capabilities not previously available. GoldenGate addresses these demands with the ability to converge on complete transceivers with the speed to enable full characterization prior to tape out.
A common theme in all RFIC design projects is a lack of complete characterization of the radio prior to tape out. This results in costly spins, missed time-to-market and has lead to companies going out of business. The primary culprits for this lack of characterization has traditionally been the inability of existing simulation tools to perform and the lack of time. GoldenGate helps reduce design spins through its capacity to simulate full transceiver chains, including parasitic views, its speed to perform these simulations extremely fast and its unique frequency-domain capabilities to perform the necessary analyses allowing designers to meet specs.
Designers are often faced with the task of not only designing a working radio, but ensuring it is highly manufacturable in volume. GoldenGate enables the designer to run extensive Monte Carlo analyses, sweeps across process corners and yield analysis. These simulations have traditionally been too time consuming to be useful given tight design schedules. GoldenGate enables these necessary analyses by providing simulation speedups orders of magnitude over traditional transient-based techniques through its unique frequency-domain capabilities.
Download the latest version of GoldenGate from the Knowledge Center: GoldenGate 4.1.10
GoldenGate 4.2.0 (Releasing May 1)
"Expanded Simulation Coverage"
GoldenGate 4.2.0 provides improved simulation throughput and expanded RF/Mixed-Signal simulation coverage needed for RFIC designers to discover problems early and prevent costly re-spins. This release provides:
- 5x speed improvement in transient simulations
- With 2x to 4x improvements on single-core computers and typically 5x for quad-core computers, reducing transient simulation times allows for more simulations runs for more simulation coverage without compromising tight development schedules
- New mixed-signal simulation capabilities include:
- Digital State Sweeping (DSS) provides an automated solution to the problem of sweeping an RF design through its many digital control states. DSS automates operational verification of the control states and provides interface and connectivity testing as well as digital-RF connectivity debugging, allowing digital and RF teams to work concurrently.
- Mixed Signal transient co-simulations of RF and Verilog-AMS digital circuits with third party digital simulator.
- Standard-complaint wireless sources for GoldenGate libraries from Agilent’s Ptolemy system simulator, including transmit/receive waveforms for 802.11(WiFi), 802.16 (WiMAX/WiMAN), TDSCMDA, 3GPPFDD, and custom, user-defined wireless sources.
- Improved Monte Carlo simulation throughput with 5-10x fewer trials using Latin Hypercube Sampling (LHS) and Hammersley Sequence Sampling (HSS)
and more!
GoldenGate 4.1.10
GoldenGate 4.1.10 includes enhanced support for Process Design Kits (PDKs) that use inherited parameters.
For more detailed information on this version of GoldenGate, refer to the product Release Notes on the Knowledge Center.
GoldenGate 4.1.9
GoldenGate 4.1.9 includes improvements in models and parallel simulations.
For more detailed information on this version of GoldenGate, refer to the product Release Notes on the Knowledge Center.
GoldenGate 4.1.8
GoldenGate 4.1.8 features a number of important enhancements including the following:
For more detailed information on this version of GoldenGate, refer to the product Release Notes.
GoldenGate 4.1.7
GoldenGate 4.1.7 features a number of important enhancements including the following:
- Support for Cadence IC 6.1.2
- Increased flexibility in viewing results
For more detailed information on this version of GoldenGate, refer to the product Release Notes.
GoldenGate 4.1.6
GoldenGate 4.1.6 features a number of important enhancements including the following:
- New Large-Signal S-Parameter (LSSP) analysis which provides the small signal equivalent S-parameters of a circuit operating under non-linear conditions.
- Support for the Cadence Analog Design Environment, Corners Tools with ability to run the multiple Corners simulations in parallel (such as GoldenGate's Monte Claro capabilities).
- New Monte Clarlo/parallel simulation cockpit (QMCC) tool. This tool enables fine tuning and monitoring of parallel simulations such as Monte Carlo and Corners. QMCC also enables viewing of the finished trail results on a per-trial basis while the simulation is running.
- GoldenGate now has the ability to read Ptolemy/Signal Studio waveform data files (*.wmf and *.sig) on Linux 32 and 64-bit systems.
For the GoldenGate 4.2 Release, RHEL 4 will be the primary operating system (OS) for GoldenGate. RHEL4 provides the needed facilities for many of the new enhanced features of GG4.2 – such as: multi-threading (key for 5x transient speed-up), support for QMCC & parallel simulations -- and for new upcoming features. Additionally with ADS 2008, GGTools 4.2 (DDS, Momentum, and Ptolemy) is not supported on some older OSs.
- What about RHEL 3 and Solaris??
- — With limited support, GG4.2 is the last major release for RHEL3 & Solaris
- — The first few follow-up releases until October 1, 2008 will provide limited support for RHEL 3 & Solaris
- — With GG4.2, some features will not be available on these OSs.
- Not supported on GG4.2:
- RHEL3: GGTools 4.2, Ptolemy wireless sources, parallel simulation/QMCC, Verilog AMS co-sim & multi-threading
- Solaris 8 & 9: GGTools 4.2, Ptolemy wireless sources, 64 bit operation , Verilog AMS co-sim & multi-threading
- Solaris 10: 64 bit operation , Verilog AMS co-sim & multi-threading
GoldenGate will continue to support license servers on RHEL3 & Solaris.
In conjunction with rest of the EEsof products, support for RHEL5 is being planned for 2009.
For general information on supported operating systems for other Agilent EEsof EDA products, refer to Software Versions, Computer Platforms, and Operating Systems.
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