Genesys Accessories - Advanced Modeling Kit

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Genesys Advanced Modeling Kit gives users the ability to add critical new active device models in an industry-standard modeling language, to achieve high-performance at low cost.

Create a low-cost competitive advantage

Genesys is a versatile, low-cost design platform with very good performance and access to 5 key simulation domains. When you add your intellectual property to the Genesys environment, it becomes a secret weapon for emerging RF designs. The Advanced Modeling Kit minimizes simulation costs and design risk for a whole workgroup by incorporating world-class, transportable IP from other researchers, industry partners, and advanced platforms into a low-cost platform that can be widely deployed at reasonable cost. It provides a Verilog-A compiler and run-time user license for DC, harmonic balance, or Spice. Verilog-A is a standard, transportable hardware description language (HDL) that connects you to the larger compact modeling community.

Typical applications of Advanced Modeling Kit

• a special Verilog-A device model from a preferred foundry partner
• a high-performance GaN transistor with self-heating from a DARPA consultant
• a uniquely accurate diode model from a modeling service provider
• a special analog, PLL, or signal integrity function block (such as a DFE pre-emphasis unit) from an external vendor
• Any user-defined model, for use with harmonic balance, or Spice

While Agilent provides other EDA platforms such as GoldenGate and ADS for high-performance, design-flow intensive physical design, Genesys remains useful to technologists and smaller workgroups doing active, smaller-scale electrical designs in the wireless and aerospace/defense frequency bands (such as WiMAX and JTRS).

Benefits of Advanced Modeling Kit

• The latest device research and foundry models give your company a timely, competitive advantage
• Self-heating and other device-specific effects allow exploration of high-performance architectures
• Extend a standard, low-cost environment (Genesys) to deliver key IP without sacrificing speed, convergence, or supportability – especially critical for cost-sensitive situations such as mobile high-contributors, remote design centers, start-ups, and consultants
• Minimize design risk by adopting proven, industry-standard models at low cost

The Verilog-A compact model interface (CMI) generates compiled code that executes at speeds comparable to C-based models, and often has superior convergence. With Verilog-A, complex custom models can be transported among several simulators quickly and easily. The Advanced Modeling Kit also includes new Verilog-A nonlinear models for 16 advanced nonlinear BJT, MOS, and MESFET models.

Figure 2: Genesys provides 16 Verilog-A models for use with Harbec and Cayenne. These and other emerging, custom models can be modified and re-compiled using the Advanced Modeling Kit for a fraction of the cost of deploying custom models on other EDA platforms.

How is Advanced Modeling Kit made available?

• Advanced Modeling Kit (AMK) will not operate properly in configurations having only linear simulation (Genesys Core). AMK may be added to any configuration or bundle containing either of the Genesys nonlinear circuit simulators (Harbec, or Cayenne)
• Advanced Modeling Kit was formerly included with the Complete Plus and Enterprise bundles from the Eagleware-Elanix company.

Advanced Modeling Kit interactions with other Genesys modules

• Advanced Modeling Kit only interacts Harbec and Cayenne, it does not affect Spectrasys, Synthesis, or the EM simulators. Other new models: TFT, JUNCAP, Varistor

Application Notes

• #22: Nonlinear Modeling of Step Recovery Diodes Using Verilog-A, May 2004

Learn how to create a full non-linear device model using the Verilog-A compiler in Genesys's Advanced Modeling Kit. This application note takes you through a step-by-step process for modeling a step recovery diode, including the simulation of a comb generator and 10X multiplier.

Additional Reference Information

• The Designer's Guide: Verilog-A Examples and Reference