E8886 Verilog-A Compiler

Verilog-A Compiler (E8886) enables the simulation of Verilog-A models in ADS/RFDE. This compiler-based solution results in simulation times comparable to built-in models. It also allows model developers to distribute models while protecting their IP. Verilog-A models that are contained within circuit schematics are compiled automatically on-the-fly without intervention by the user. These models can be run in any of the analog/RF simulators in ADS and RFDE (Linear, Transient, Harmonic Balance, Circuit Envelope) as long as the Verilog-A code contains the appropriate time domain and/or frequency domain functions. Verilog-A can be used to create behavioral models of RF blocks such as mixers, amplifiers, etc., as well as transistor models for MOSFETs, BJTs, HBTs, etc. Many transistor model examples are provided with the product, and can be used as the basis for more complete device models. Click on the following links for complete information. Product Information Ordering and Configuration Product Literature

Product Description

What is Verilog-A?

Verilog-A is an IEEE standard analog hardware description language. It is specifically designed for modeling behavior of analog components.

ADS and RFDE both provide a Verilog-A solution in which the simulation speed is close to built-in C models and IP is protected due to compiled code. All EEsof analysis types also support Verilog-A.

Note. In general, Verilog-A modules that employ event-driven operators such as timer or cross cannot be simulated in Harmonic Balance.

Verilog-A Solution in ADS and RFDE

The Verilog-A compiler technology in ADS and RFDE hides all of the complexities. It looks like an interpreter to an end-user and no understanding of the compiler is required. The solution is supported by all EEsof analysis types and allows models to be developed once and run in any simulation environment.

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Verilog-A Compiled Model Used in Simulation

Verilog-A support in ADS and RFDE allows the designer to create Verilog-A behavioral and compact models within the Cadence Virtuoso Design environment.

Spectre Compatible Verilog-A Based Cell Views

Spectre compatible Verilog-A based cell views are supported in RFDE. If Verilog-A fragments exist in the Cadence environment, they can be easily be ported to ADS environment. RFDE users can use Cadence Verilog-A UI support to create Verilog-A based components, which they can subsequently use in an RFDE simulation.

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PLL Circuit with Components Modeled Using Verilog-A

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Verilog-A Based Cellview in RFDE

Why is Compiled Verilog-A Solution Important to Customers?

Major Benefits

• Verilog-A is an industry-standard, portable analog modeling language
  
• Customers can now create new models for cutting-edge technologies.
  
• Solution is compile-complete; the simulation speed is close to built-in C-based models.
  
• Compiled code is in binary format and transporting this code will protect the user's IP.
  
• Users can also modify existing models with enhancements using Verilog-A and can override the existing built-in model.
  
• Compiler hides all the complexities - user can concentrate on writing the Verilog-A code and not worry about transporting it to the simulator.
  

Verilog-A Target Applications

Circuit Design

• Transistor models
  
• Custom component models in PDKs
  
  • Passive components, nonlinear resistors, capacitors, inductors
    

A/RF System Design

• Behavioral models for mixers, amps, PLLs, oscillators, etc.
  

Tiburon Design Automation

The Verilog-A compiler in ADS and RF Design Environment is based on technology from Tiburon Design Automation. For more information, click on the following link:

• Tiburon Design Automation
  

How To Buy

To request immediate sales assistance - for help choosing the best system; for product configuration and integration details; to request telephone assistance or an on-site demo of the software; or to request a price quotation - click on the following link:

• Agilent EEsof EDA Sales Assistance

Product Literature

• E8886A Verilog-A Compiler (PDF file, 171 KB)
  

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