Example: Early Detection of Algorithm Design Problems in an FPGA Interleaver

This case study shows a real-world example of an FPGA algorithm issue detected late in the system hardware integration testing phase. The cause of the issue was unknown and difficult to diagnose. It was initially unclear as to whether the issue resided in software or in the FPGA hardware.

The issue was diagnosed and resolved by comparing the FPGA test vectors with the simulated test vectors from pre-configured C/C++ baseband blocks in the 1XEV-DO Wireless Library as shown below. This process revealed that a bit reversal was occurring in the FPGA interleaver algorithm.

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This algorithm issue was difficult and time-consuming to diagnose and resolve while in integration testing. An improved approach, which is illustrated below, could have instead helped to identify and resolve this issue much earlier in the simulation design phase:

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Test vectors from algorithms written in C or C++, MATLAB®, Verilog or VHDL, or constructed and simulated with float or fixed-point baseband simulation blocks in the Wireless Libraries to verify algorithm functionality early in the simulation design phase. The example illustrated above is a Mobile WiMax example.

This can help minimize integration risk by identifying potential issues earlier in the simulation design phase (where they are relatively easy to fix), rather than later in the system integration testing phase (where they are more time-consuming and costly to fix). .

Product Details

• Agilent Ptolemy Matrix Models - MATLAB® cosimulation
• HDL Co-Simulation - Verilog or VHDL
• Agilent Ptolemy - floating point simulation blocks
• Agilent Ptolemy Fixed Point Analysis - fixed-point model analysis and optimization
• Wireless Libraries
• Connected Solutions

Other Communications System Design Examples ...

• WCDMA Transmitter Design and Verification
• LFM Chirped Radar Design and Verification
• Mobile WiMax PER Measurement