Flow Diagram - Communications System Design
Click on the system flow diagram below for details about each stage in the design process:
Flow Diagram
|
Next Section
|
Top of Page
Algorithm Exploration/ Architectural Design
Communication System algorithms need to be constructed at a fairly high level of abstraction and evaluated in a complete end-end system context. At this level the overall system is abstractly modeled with a few key impairments to facilitate more detailed development of key algorithms.
These key algorithms are either written in C/C++ and/or M-File format or modeled graphically via commercially available baseband behavioral models. RF/Channel impairments are typically modeled behaviorally with transmitter, receiver, and multi-path/fading models to quickly understand the overall system design performance.
System integration risk can be minimized by:
- Co-simulating key algorithms written in MATLAB® or with C-code algorithms together with RF behavioral models to identify potential system integration issues earlier.
- Constructing communications algorithms with block-level development tools. This is easy to do using the SystemVue family of products.
- Introducing channel impairments with preconfigured antenna and propagation model sets. These eliminate the need to invest costly engineering time in writing or developing custom models.
- Comparing algorithm test vectors with pre-configured baseband C/C++ blocks in the Wireless Libraries to ensure that algorithm development is on track early in the product development lifecycle.
- Verifying key metrics such as EVM and coded BER/PER of system designs and key algorithms by using the pre-configured baseband simulation capability in the Wireless Libraries.
Related Examples
Next Section
|
Flow Diagram
|
Top of Page
RF Architecture Design
RF transmitter and receiver block level designs can be constructed using a rich set of RF parameterized behavioral models, specifying parameters such as gain, 1-dB compression point, third-order intercept point, noise figure, and others. Cascaded budget analysis may be performed, evaluating the RF system performance at every stage (e.g. valuating the effective cascaded input NF of an RF receiver design). Spurious analysis may be performed to evaluate various frequency management schemes and filtering requirements for upconversion or downconversion in an RF transceiver.
System integration risk can be minimized by:
- Verifying key metrics such as EVM and coded BER/PER of RF designs by using the pre-configured baseband simulation capability in the Wireless Libraries.
- Verifying RF designs with co-simulated baseband algorithms to help identify potential integration issues early in the simulation design phase. The baseband algorithms can be written in C or C++, MATLAB® algorithms, Verilog or VHDL, or constructed and simulated with float or fixed-point baseband/math simulation blocks.
Related Examples
Previous Section
|
Next Section
|
Flow Diagram
|
Top of Page
RF Circuit Implementation
System-level verification can even be extended into the RF Circuit Implementation Phase as part of an RFIC or an RF Board flow.
System integration risk can be minimized by:
- Co-simulating the transistor-level circuit designs at a system level to verify system-level performance of circuits as the circuit design phase progresses
- Verifying key metrics such as EVM and coded BER/PER of co-simulated RF circuit designs by using the pre-configured baseband simulation capability in the Wireless Libraries.
- Co-simulating transistor-level RF circuit designs with co-simulated baseband algorithms to help identify potential integration issues early in the simulation design phase. The baseband algorithms can be written in C or C++, MATLAB®, Verilog or VHDL, or constructed and simulated with float or fixed-point baseband/math simulation blocks.
Related Examples:
Previous Section
|
Next Section
|
Flow Diagram
|
Top of Page
Baseband Architecture Design
As baseband algorithms are written for each block in a coding/decoding chain, system integration risk can be minimized by:
- Co-simulating baseband algorithms written in C or C++, MATLAB® or constructed and simulated with float or fixed-point baseband/math simulation blocks with RF behavioral models to identify potential system integration issues earlier.
- Performing detailed fixed point analysis of constructed algorithms and create VHDL for rapid prototyping. These tasks are easy using the SystemVue family of products.
- Introducing channel impairments with preconfigured antenna and propagation model sets. These eliminate the need to invest costly engineering time in writing or developing custom models.
- Comparing algorithm test vectors with pre-configured baseband C/C++ blocks in the Wireless Libraries to ensure that algorithm development is on-track early in the product development lifecycle.
- Verifying key metrics such as EVM and coded BER/PER of system designs and key algorithms by using the pre-configured baseband simulation capability in the Wireless Libraries.
Related Examples
Previous Section
|
Next Section
|
Flow Diagram
|
Top of Page
Baseband Algorithm Implementation
As baseband algorithms for your communications architecture move towards implementation, system integration risk can be minimized by:
- Co-simulating baseband HDL written in Verilog or VHDL with RF behavioral models to identify potential system integration issues earlier.
- Generating C-Code Models for floating-point algorithms directly from block level algorithm for implementation in embedded DSP.
- Generating VHDL for fixed point algorithms directly from block level description for rapid prototyping in FPGA.
- Introducing channel impairments with preconfigured antenna and propagation model sets. These eliminate the need to invest costly engineering time in writing or developing custom models.
- Comparing algorithm test vectors with pre-configured baseband C/C++ blocks in the Wireless Libraries to ensure that algorithm development is on track early in the product development lifecycle.
- Verifying key metrics such as EVM and coded BER/PER of system designs and key algorithms by using the pre-configured baseband simulation capability in the Wireless Libraries.
Related Examples
Previous Section
|
Next Section
|
Flow Diagram
|
Top of Page
Communication System Integration Testing
As the product lifecycle transitions from design simulation to hardware testing, Agilent's Connected Solutions can be used to help minimize system integration risks by combining simulation and test instrumentation capabilities. System integration risk can be minimized by:
- Using simulation models to represent missing RF or baseband hardware, so that system level testing can begin earlier- before final hardware integration testing.
- Verifying the coded BER or PER performance of standalone RF hardware (without baseband hardware), using simulated baseband capability in Wireless Libraries to represent missing baseband hardware functionality.
- Introducing simulated signal impairments such as multipath or fading into hardware test signals, to help identify potential system performance issues earlier.
- Using simulation to create custom or proprietary signal formats, for emerging wireless or aerospace/defense applications.
Related Examples:
Previous Section
|
Flow Diagram
|
Top of Page
 top of page
 printer-friendly version
 email this page
|
Contact Us
