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Hurdle the gigabit per second barrier
Increasing consumer and business demand for digital entertainment and information transmission is driving the need for high-speed systems such as routers, servers, mass storage system, and PCs. Chip-to-chip connections inside these systems have undergone an architectural shift from parallel busses to serializer/ deserializer (SERDES) links called lanes. Such serial links eliminate parallel bus clock skew and reduce the number of traces — advantages that come at the cost of large increases in bit rate on the remaining traces. At multigigabit per second data rates and with channel flight times longer than a bit period, signal integrity is a major concern. Under these conditions, high-speed analog effects, previously only seen in high frequency RF and microwave engineering, can impair the signal quality and degrade the bit error rate of the link.
Agilent EEsof EDA has for years been proud to offer Advanced Design System (ADS) as the premier simulator of RF and
microwave effects. RF and microwave engineers trust ADS to analyze their circuits and to help them mitigate the impairments encountered at these frequencies. Now, through continuous research and innovation, Agilent EEsof EDA offers three ADS bundles that put the applicable simulators, libraries, and capabilities into the hands of signal integrity engineers.
These bundles, listed on the Signal Integrity Products Page, provide the most complete serial link analysis for standards such as Infiniband, PCI Express, RapidIO, DDR, HDMI, and 10 gigabit/s Ethernet. They allow you to:
- Analyze complete serial links by co-simulating individual components, each at its most appropriate level of abstraction: link-, circuit- or physical-level.
- Import S-parameters accurately into transient simulations.
- Perform jitter diagnosis with the proven EZJIT Plus algorithm used in Agilent instruments, resulting in dramatically reduced product design cycles.
Click on the "Products" tab above to see a table of links to the product pages for the modules that make up these bundles.
Features at a Glance
The Advanced Design System allows you to perform Signal Integrity analysis of designs involving Infiniband, PCI Express,
RapidIO, Serial ATA, DDR3, 10 Gigabit Ethernet and more.
- ADS High Frequency SPICE simulator—simulate band-limited S-parameter models accurately.
- Verilog-AMS co-simulation—accurate simulation of SERDES models.
- HSPICE compatibility—direct simulation of HSPICE driver/receiver netlists.
- Exhaustive Jitter and BER analysis using Agilent patented EZJIT Plus technology.
- Stateye-based fast BER simulation.
- SERDES components (8B10B, 64B66B Encoder/Decoders, decision feedback (DFE) and feedforward (FFE) equalizers.
- IBIS I/O Models.
- W-element model simulation.
- Link with Cadence Allegro and Mentor Expedition tools.
- Patent pending Broadband SPICE Model Generator.
- Exhaustive library of multilayer transmission line models and other interconnects.
- Powerful post-processing for automated Eye-diagram and jitter measurements.
- Encrypted HSPICE simulation.
- Integrated full-wave Method of Moments and Finite-Element solvers.
- Wide variety of digital sources, including jitter.
- Types of simulations available: S-parameter, AC, Time-domain, Envelope, Electromagnetic, Signal processing.
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