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Agilent EEsof EDA helps you in your RFIC design process by providing:
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Successful RFIC design flows
The keys to success in creating an efficient, thorough RFIC design flow include:
- Design verification throughout the design process, not just at the end - and with specification-compliant non-sinusoidal signals. When verification occurs only at the end of the design process, or not until tape-out, corrections can be costly and time-consuming. Verification includes simulation of the extracted views to include the effects of parasitics as well as the ability to run Monte Carlo or corner analysis to investigate manufacturing variations.
- Simulation speed and capacity are essential in order to handle the increasing complexity (both in number of devices and number of parasitic elements) of RFICs. Simulators must be able to complete simulations of large extracted views in a reasonable length of time, or designers won't run them, leaving their designs at risk.
- Data display and post-processing capabilties that support the full range of analyses required for complete circuit and system characterization. Limited, generic display and post-processing options produce corresponding limits in design insight.
- Experienced, knowledgeable technical support and consulting, to help integrate diverse design tools, processes, and foundry Process Design Kits.
- Integration with the Cadence design flow, if desired.
- Process Design Kits (PDKs) and foundry support to carry designs from prototype to manufacturing.
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Design verification thoroughout the design process
- RFIC system designers need to be able to do top-level design with behavioral models, and then verify that they work with transistor-level designs, or with behavioral models derived from the transistor-level designs.
- The designers of each RFIC circuit at the transistor level need to be able to verify that each circuit (and the whole design) works with specification-compliant signals, not just sine waves.
- System designers need to be able to transfer new and custom specification-compliant simulation setups and measurements to circuit designers so they can verify that their circuits work with these non-sinusoidal signals.
- Block-level designers need to be able to simulate extracted views to include the effects of parasitics as well as run Monte Carlo or corner analysis to investigate manufacturing variations.
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Simulation speed and capacity
Limits on the type, range, or capacity of simulation tools can impose major limits on accuracy, flexibilty, and design exploration.
- RFIC circuit designers need to be able to sweep and optimize parameters for best third-order intercept (IP3), conversion gain, phase noise, tuning range, and other specifications.
- When goal specifications are best defined as a function of spectral components in the frequency-domain - IP3, conversion gain, and power-added efficiency, for example - frequency-domain simulation should be used.
- Simulation capabilities should be able to handle large circuits with extracted parasitics and highly non-linear designs such as dividers. Fast, powerful simulators, in general, enable more "what-if" analyses early in the design process.
- Designers should be able to simulate signals at whatever frequencies they want. They should not be forced to shift signal frequencies around due to limitations of their simulators.
- RFIC circuit designers need to be able to run EM simulations on arbitrary layout structures to get more accurate results than can be obtained only with analytical models. These simulations should be fast, and re-use of the data in other simulations should be both simple and fast.
- Simulators must be able to complete simulations of large extracted views in a reasonable length of time, including Monte Carlo or corner analysis to investigate variability.
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Powerful post-processing capability
Circuit and system designers need flexible and powerful ways to display simulation results, to enable better analysis and design decisions.
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Models and libraries
RFIC system and circuit designers need access to a wide range of models and components for both generating and measuring signals and for modeling circuits.
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Technical support and consulting
The complexity of RFIC design makes access to experienced technical support and consulting very nearly a requirement. With PDKs from various IC fab houses, and various tools from different EDA vendors, RFIC design can be complex. Sometimes designers need technical assistance to get everything to work.
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Process design kits and foundry support
Agilent EEsof EDA simulators support design kits from all major RFIC foundries. Our GoldenGate, RFDE and ADS dynamic link simulators directly simulate the models from Spectre PDKs. Because these foundry kits are developed and maintained by the foundry, they provide the best compatibility with the foundry process, the latest foundry kit upgrades at the soonest possible time, and can provide design automation features to speed the design process.
Some foundries also provide dedicated ADS design kits. The foundry partners listed provide silicon design kits for use in ADS RFIC design flows.
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RFIC foundry partners
Agilent EEsof EDA's RFIC foundry parterns include:
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Customer comments
"Micro Linear used ADS to behaviorally model a direct FSK modulator at 5.8GHz. Since the modulator was based on a fractional-N synthesizer with a two-port VCO, we were concerned about the interaction between the modulation signal and loop filter of the fractional-N synthesizer.
ADS gave us the capability to run mixed signal simulations that involved both analog blocks, such as the loop filter, and digital blocks such as the delta-sigma modulator and Gaussian pulse-shaping filter. These simulations were crucial in optimizing important design parameters such as PLL configuration and loop bandwidth.
Moreover, the simulation helped us to gain much better insight into the influence of the DSM architecture on the quantization noise of the synthesizer. After verifying our digital blocks at the algorithm level using Ptolemy, we used the HDL co-simulation capability of the ADS to validate our Verilog codes for the DSM and the pulse-shaping filter. The chip was built in a SiGe BiCMOS process and we were impressed by how closely lab results matched ADS simulation."
-- Shayan Farahvash, RFIC Systems Architect, Micro Linear Corporation, San Jose, California, USA
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Request a demo
Request a demonstration of GoldenGate Plus - RFIC Design Solutions.
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