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Example 1: Verification and troubleshooting: Receiver with WLAN 802.11 signalIn RFIC design, design verification is essential throughout the design process, not just at the end - and it should be done with specification-compliant non-sinusoidal signals. When verification occurs only at the end of the design process, or not until tape-out, corrections can be costly and time-consuming. How do you verify that the blocks (amplifiers, mixers, frequency dividers, baseband chains) in your RFIC are wired together correctly? Which block causes the most signal degradation? Where should you focus your efforts if you need to improve BER? This schematic shows a direct-conversion receiver from the Agilent RFIC Flow Workshop. This schematic shows a direct-conversion receiver from the Agilent RFIC Flow Workshop.
It consists of an LNA, I and Q mixers and baseband receive chains, and a frequency divider to generate quadrature LO signals. We want to supply a WLAN 802.11b input signal to the LNA, and verify that the I and Q baseband output signals still track the input modulation, at various points along the baseband chain (outputs from the mixers, outputs from the DC offset cancellation circuit, outputs from the VGAs and from the tunable filters.) The simulation uses time-domain baseband data sources that are the I and Q data of a WLAN 802.11b signal. These data sources modulate a sinusoid via an ideal modulator to generate the test signal at the input. If you have the I and Q time-domain data waveforms for some other modulation format, you may use this technique along with the Circuit Envelope simulator to generate a modulated test signal. The simulation time required depends linearly on the desired stop time, with about 10 minutes being the minimum to get useful information. The circuit has 2547 devices, 1377 of which are nonlinear. The data display shows comparisons between the input signal and the signals at various points in the receive chain. By changing the Vtest equation, you can select the test point to be the output of the mixer, the output of the DC offset cancellation circuit, the output of the first variable gain amplifier, or the output of the baseband filter. The plots compare the spectra, magnitudes, phases, real and imaginary parts, and the trajectories of the input and Vtest signals.
The data display also calculates the "generic" EVM, which is the result of including every time point (not just the symbol samples) in the EVM calculation. By changing the Vtest equation, you can see if there is a block in the receiver chain that significantly degrades the EVM. Also, you can make changes to various blocks to see if the EVM can be improved. A good strategy for minimizing BER is to first run relatively quick simulations like this to test the EVM. When the EVM is minimized, the BER should be minimized as well, and these EVM simulations are much faster than simulating BER. Using this type of simulation, you can easily see whether your receiver or transmitter is wired up correctly and which block is causing degradation. For More Information ...For more information on the design and the simulations in this example, contact your Agilent EEsof EDA representative for details on downloading a copy of the fully-functional RFIC Flow Workshop. Top of PageExample 2: Simulation of the output power and EVM of a power amplifierRFIC design requires that each circuit (and the whole design) meets its performance goals with specification-compliant signals, not just sine waves. In RFIC power amplifier design, the desired performance is typically specified in terms of output power, EVM, CCDF curves, constellation diagrams, and other measurements using signals such as an 802.11b WLAN signal. Power amplifier design involves a number of steps, including device characterization, load pull, matching network design, gain compression, frequency response simulation, gain compression simulation, third-order intercept simulation, and other measurements. These may all be carried out efficiently with RFDE with simple sinusoidal test signals. But ultimately the amplifier must deliver the desired output power while satisfying the EVM specification. You can’t test for this with sinusoids. You have to use an 802.11b signal and need to be able to make the required measurements (output power, EVM, CCDF curves, constellation diagrams, etc.) Power amplifier designers don’t want to be required to know all the details of generating these signals and making these measurements. So the Wireless Test Bench capability within RFDE takes care of these details for you. You just specify the input and output nodes, the type of signal (WLAN 802.11b transmit, in this case), and the desired measurements (RF envelope, constellation, power, spectrum, EVM), and the Wireless Test Bench runs the simulation, makes the measurements, and plots the results.
The Wireless Test Bench runs a co-simulation using the Ptolemy simulator to generate the test signal and make the measurements, and the Circuit Envelope simulator to accurately simulate the transistor-level subcircuit.
This is the power amplifier subcircuit, with the blocks on the right Momentum (EM) models of the spiral inductors.
The simulation uses Automatic Verification Modeling (explained in the Circuit Envelope Simulation Theory of Operation), a technique that speeds up (sometimes by several orders of magnitude) simulation. When this mode is enabled, the analog subcircuit is first characterized using a variety of Harmonic Balance simulations at the start of every Ptolemy simulation. Then during the actual Ptolemy simulation, this characterization data is used to predict the response of the subcircuit instead of performing the full circuit simulation at each time point. A simulation of 10 frames of data requires only about 43 seconds. Plots like this spectrum and EVM data are generated automatically when the simulation finishes. It is also possible to sweep the input power and generate an EVM versus output power curve.
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For more information on the design and the simulations in this example, contact your Agilent EEsof EDA representative for details on downloading a copy of the fully-functional RFIC Flow Workshop. Top of PageExample 3: Optimization of mixer IP3 and conversion gainIn RFIC design, limits on the type, range, or capacity of simulation tools can impose major limits on accuracy, flexibilty, and design exploration. If the goal specifications are best defined as a function of spectral components in the frequency-domain - examples include IP3, conversion gain, and power-added efficiency - frequency-domain simulation such as harmonic balance should be applied. Example: Harmonic Balance Simulation and Optimization of Mixer IP3 and Conversion GainWith harmonic balance, performance characteristics that need to be computed from the spectrum may be simulated and optimized very easily. Among these is IP3 (Third-Order Intercept Point). Try doing this with a time-domain simulator and you are likely to run into two big problems:
Harmonic balance simulation is far superior to time-domain simulation for this type of simulation. Optimization Variables and SetupThis example simulation varies three design variables, different device widths, to maximize the voltage gain and the IP3 point. To run an optimization, you have to define which parameters (optimization variables) the optimizer can vary, define the responses to be optimized, and choose the optimization algorithm. The optimization controller window is shown here:
The equations that define the optimization goals are as follows:
Spectrum is the differential voltage spectrum at the output nodes Voutp-Voutn. Vinput_dB is the differential voltage at the input nodes, Vifp-Vifn, at the 0,1,0 mixing tone. The frequency of this 0,1,0 mixing tone is determined by how you have specified the fundamental tone frequencies on the harmonic balance simulation controller. In this case, #1 is Flo, #2 is Fif1, and #3 is Fif2, where Flo, Fif1, and Fif2 are design variables. So the 0,1,0 mixing tone is Fif1, the 1,1,0 tone is Flo+Fif1, and the 1,-1,2 mixing tone is Flo-Fif1-2*Fif2. In this way the lower-sideband third-order intermodulation distortion term at the output, IM3_LSB, is defined. V_gain_LSB is the desired voltage conversion gain from the lower sideband input to the lower sideband at the output (assuming that Fif1 < Fif2.) TOIoutput_low is the output third-order intercept point, calculated from a simple, graphical extrapolation from the amplitudes of the desired signal and undesired intermodulation distortion term. A quick parameter sweep (4 values requires just 73 seconds) simulation may be used to determine which parameters have the biggest effect on the desired responses.
This shows that the gate width of one of the current source devices, has a strong effect on the input-referred IP3 point (here named TOIin…) but only a slight effect on the conversion gain. Optimizations can take much longer to run, depending on the number of optimization variables, the number of goals, how long it takes a single simulation to run, and the optimization algorithm. This optimization, with 10 random iterations, required about 26.5 minutes, and shows a significant improvement in both the conversion gain and the IP3 point (here labeled TOIoutput_low.)
For More Information ...For more information on the design and the simulations in this example, contact your Agilent EEsof EDA representative for details on downloading a copy of the fully-functional RFIC Flow Workshop. Top of PageExample 4: Extracted view simulations of a power amplifierRFIC circuit and system designers need a flexible and powerful method of displaying their simulation results. This enables better analysis and design decisions. The ability to simulate and display extracted views is particularly important. Example: Extracted View Simulations of a Power AmplifierA simulator used in an RFIC flow must have the capacity to simulate extracted views. Simulation SetupThis example shows a 1-dB gain compression simulation of the 250,000-parasitic element extracted view of a power amplifier. A 1-tone source is used as the test signal, and its power is swept, with the initial value very low (-105 dBm.) With this low input power level, the amplifier is very nearly linear, so it does not generate any harmonics and harmonic balance converges relatively easily. The input power level then may be increased in large steps (15 dB, for example), until the amplifier starts to compress, at which point finer steps (1 dB, then 0.5 dB) are used. The simulator maintains convergence because it uses the solution at the previous value of the swept parameter (the input power in this case) as an initial guess for the solution at the current value of the swept parameter. The total simulation time required for the sweep was about 1 hour and 8 minutes, and it required 900 Mbytes of RAM. Data Display: Power Gain, Gain Compression
In this data display, the swept variable is RF_Power, the input power in dBm. The output power at the 1-dB gain compression point is 21.081 dBm. This appears in the right-hand plot, Gain Compression versus Output Power, where PAE is plotted as the red trace. Marker m1 is currently set at 1 dB, where the x-axis value of indep(m1) is 21.081. The power-added efficiency (PAE) is shown in the left-hand plot, Power Gain versus Input Power. The blue trace gives the PAE, and it shows that the 1-dB gain compression point occurs at an input power of -2.3 dBm. This is the x-axis value RF Power=-2.300 of marker m3 The equations show power, gain, gain compression, DC power consumption, power-added efficiency, and interpolated results. The interp( ) function interpolates between actually-simulated data points to enable you to determine values such as the 1-dB gain compression point more easily. Data display files may be saved as templates and reused, saving you lots of time and enabling different designers to display results in a consistent way. Data Display: S-Parameter Frequency ResponseAn S-parameter frequency response simulation of the extracted view requires only about 15 minutes and 20 seconds, for a sweep from 2 to 3 GHz, in 25 MHz steps. This requires only about 430 Mbytes of RAM.
For More Information ...For more information on the design and the simulations in this example, contact your Agilent EEsof EDA representative for details on downloading a copy of the fully-functional RFIC Flow Workshop. Top of PageExample 5: Efficiently simulating a direct-conversion receiver or transmitterRFIC designers need the most efficient simulators for each task. They need frequency-domain tools for steady-state simulations, time-domain tools for transient simulations, and mixed frequency- and time-domain tools for simulations of modulated signals or transient control signals in the presence of RF. These include phase-locked loops and automatic gain control circuits. Simulation of direct-conversion transmitters and receivers should be easy, in spite of the very large difference between signal frequencies. Example: Efficiently Simulating a Direct-Conversion Receiver or TransmitterDirect-conversion receivers and transmitters are becoming common. Because of the large difference in signal frequencies - an LO and its harmonics must be simulated along with baseband signals near DC - time-domain simulators cannot simulate such circuits efficiently. Harmonic Balance and Circuit Envelope simulators are well suited for circuits of this type because both are frequency-domain simulators. Circuit Envelope has the additional advantage of requiring only one fundamental tone, and thus uses less memory. Circuit Envelope is also able to simulate both steady-state responses and modulated and/or transient signals. Harmonic Balance is limited to steady-state responses. Downconversion SpectrumThe spectrum for a direct downconversion is shown below. There are two input signals (RF tones) near the LO frequency, with downconversion to baseband terms at the output.
This simulation could be run using either Harmonic Balance or Circuit Envelope, because the simulated signals are sinusoids, their harmonics, and mixing tones. With Harmonic Balance, this simulation would require three large-signal tones, one for the LO and one for each RF signal. A two-tone simulation can also be used if the frequency difference between Flo and Frf1 is an integer multiple of the frequency difference between Frf1 and Frf2. With Circuit Envelope, only one large signal tone, for the LO, is required. Circuit Envelope simulation is a hybrid time- and frequency-domain simulation technique. Signals that are within the envelope bandwidth that is centered on each large-signal analysis tone are generated without requiring any additional large-signal analysis tones. The envelope bandwidth is equal to 1/(simulation time step). Tones that are within 0.5/(simulation time step) above 0 Hz are also generated. The large-signal analysis frequencies in this Circuit Envelope simulation are the LO frequency and its harmonics. The LO signal can be generated by an oscillator and/or a frequency divider, in which case its frequency is determined automatically by the simulator while solving the oscillator and frequency divider. Simulation ResultsThe following data display from a Circuit Envelope simulation using ADS/RFDE shows the results of simulating a downconverting mixer. The RF tones are at 2.44875 and 2.44900 GHz, and the LO is at 2.45 GHz.
The equations show how a particular spectral tone can be plotted as a function of the input signal amplitude. The design variables Flo, Frf1, and Frf2 specify the spectral tone. The input signal amplitude is VRFamp_dB. The simulation required about 4.5 minutes. For More Information ...
For more information on the design and the simulations in this example, contact your Agilent EEsof EDA representative for details on downloading a copy of the fully-functional RFIC Flow Workshop. Top of PageExample 6: Displaying simulation resultsTo make the best possible design decisions, RFIC circuit and system designers need a flexible and powerful method of displaying and analyzing simulation results. The data display tool should enable you to view your results and carry out calculations on them in whatever format you desire. It should not restrict you. Example: Displaying Simulation ResultsRFIC circuit and system design requires a very great range of possible data display and analysis capabilties. Each type of device has its own set of specifications and figures of merit, and insight into circuit performance often depends on being able to perform complex post-processing operations on simulaton data after it has been obtained. RFDE and ADS have the same, very powerful data display tool. There are literally hundreds of examples in ADS (although not as many in RFDE) that show its capabilities. You may use data displays from ADS in RFDE and vice versa. You may save data displays as templates and use them to display other simulation results, so you don't have to re-create them each time. The Wireless Test Benches in RFDE automatically display simulation results, such as EVM, envelope waveforms, constellation diagrams, spectra and spectral masks, etc. The data display allows you to plot data in many formats, including plots and listing columns. It allows you to place equations, place markers on the plots and use the markers in equations. You may use markers to "index" into the data after having run a parameter sweep, in which case the trace(s) will correspond to the swept parameter value chosen by moving a marker. This allows you to collect a lot of data from a swept simulation, then analyze it carefully afterwards. You may display data from multiple different simulations (even measurements) on the same plot. The data display files have multiple pages, so you may hide equations on one page and just have plots on another. You may export data to text files for post-processing using other programs. Typical Data DisplaysThe following examples show typical data displays used in RFIC design. Scroll down to study each example or click on one of the following links to jump directly to a particular display. Oscillator SimulationThe following data display shows oscillator simulation results, including harmonic balance steady-state waveforms, the turn-on transient, output spectra, fundamental frequency, and tuning sensitivity.
Return to Data Displays List Next Resonator ImpedanceThe following data display shows resonator impedance simulation versus frequency, with the tuning voltage swept as a parameter. The resonator Q is calculated using equations and marker readouts.
Previous Return to Data Displays List Next VCOThe following data display shows the frequency and amplitude variation of the VCO, as the temperature and tuning voltages are swept. The two lower plots are just a different way (order of the two independent variables swapped) of viewing the same data in the two upper plots.
Previous Return to Data Displays List Next Mixer Simulation ResultsThe following data display shows mixer simulation results.
Previous Return to Data Displays List Next Amplifier Gain Compression Simulation ResultsThe following data display shows amplifier gain compression and IP3 point simulation results.
Previous Return to Data Displays List Next Tunable FilterThe following data display shows the frequency response of a tunable filter.
Previous Return to Data Displays List Next Amplifier LoadpullThe following data display shows power amplifier load-pull contours.
Previous Return to Data Displays List Next Low-Noise Amplifier Gain, Noise, and Stability CirclesThe following data display shows LNA gain, noise, and stability circles.
Previous Return to Data Displays List Next IP3 Point Extrapolation
Previous Return to Data Displays List Next Corner Analysis, with Limit Lines
Previous Return to Data Displays List Next Comparison of Ideal Input and Test SignalsThe following data display compares ideal input and test signals at a particular test point along the receive chain.
Previous Return to Data Displays List For More Information ...Top of PageRequest a demoRequest a demonstration of GoldenGate Plus - RFIC Design Solutions. Top of Page |
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