Example: MMIC Design Enhancements Using Statistical Design Tools

Statistical design tools are essential in modern GaAs Ic / MMIC design, to achieve the best possible balance between performance and manufacturing yield.   » details

Example: MMIC Design Enhancements Using Statistical Design Tools

Process variations can turn a seemingly great MMIC design into a failure. The high costs of wasted fabrication trials and extra design iterations make designing for high manufacturing yield as well as electrical performance an essential part of modern IC design. Robust designs that are insensitive to variations in the manufacturing process are essential.

Advanced Design System (ADS) offers MMIC designers a suite of highly advanced statistical tools that provide added design insight, help to eliminate manufacturing process variation surprises, maximize product yield, and produce robust MMIC designs from the very first iteration.

Among these tools are Programmable Optimization, Sensitivity Analysis, Yield, Yield Optimization (also known as Design Centering), Design of Experiments (DOE), and Yield Sensitivity Histograms.

Working together with the powerful data display capabilities in ADS, these statistical design tools enable MMIC designers to create many useful statistical plots and histograms.

Sensitivity Analysis

The following data display from ADS shows a sample output from a Sensitivity Analysis run. The sensitivity to Noise Figure is displayed as a function of all of the design components.

As would be expected, the input matching network components contribute the most to the Noise Figure sensitivity.

Unlike DOE and Yield Sensitivity Histograms (described below), Sensitivity Analysis is local and is a function of each element in the design without interactions between the elements. In contrast, DOE and Yield Sensitivity Histograms do exhibit full interaction analysis between all the components in the design.

It is also worth mentioning that ADS Sensitivity analysis displays automatic normalization of the analysis output. The output sensitivities of different types of selected components in a design can be normalized with respect to each other.

This allows for accurate and instantaneous determination of the elements sensitivities in a design that contains various types of elements with different ranges of values such as Kohm, picofarad, micro meter, and the like.

Design of Experiments (DOE)

Design of Experiments (DOE) is a statistical tool that allows users to simultaneously study the individual and the interactive effects of many design factors. Any parameter value that could affect the output results can be evaluated.

DOE allows the designer to fully understand and evaluate the effect of individual design elements and the interaction between these elements. DOE helps determine the troublesome elements (Red X components) that are sensitive and contributes to low yield. As a result, designers can easily fix these problems and make any standard design more robust.

The following data display is a sample output of a DOE run that displays the main effects and the interactions of a MMIC amplifier S22 specification.

The Pareto plot indicates that 75% of the S22 variation is coming from the output matching network, which makes sense. 22% of the variation is coming from the Interstage network and 3% of the variation is coming from the interactions between the output matching network and Interstage network.

Next we must know the actual value of this 75%. Does this 75% contribute to 1 dB variation? Or 3 dB variation? Or 10 dB?

The following interaction plot shows that this 75% contributes to a total of 3 dB variation. This is large enough to make the S22 specification fail. Therefore, the output matching network is determined to be very sensitive and needs to be redesigned with a more robust topology.

Monte Carlo Yield and Yield Optimization

As Monte Carlo Yield analysis predicts the performance yield of a design by randomly varying its nominal component values around their manufacturing process variation, Yield Optimization (or Design Centering) automatically moves and adjusts these nominal component values as to increase the predicted manufacturing yield.

This powerful feature can be applied to both linear and nonlinear circuits and systems. It employs a technique called design centering, in which the end result is a design with nominal component values that are simultaneously centered in a way that maximizes the output yield.

Statistical Design Histogram Function in Data Display

This Statistical Histogram Function with automatically built-in equations provides measurement histograms or sensitivity histograms after any statistical Monte Carlo run. The powerful data display commands in ADS allow the creation of many useful statistical plots and histograms.

Using these histograms allow designers to investigate the whole design sensitivity and yield with respect to each individual component in the design, one by one, and without having to re-simulate each time.

The following data display is a sample Yield Analysis run that shows that the overall Yield is less than 9% (Unacceptable).

Applying the statistical Histogram to this yield run allows us to view that overall Yield as a function of each component in the design.

This display shows that the input matching network Capacitor C1 is not sensitive and the yield does not change as C1 is varied. On the other hand, R3 and the interstage matching network capacitor C1 show a slope in their yield. This indicates that the overall yield can be increased by adjusting the nominal values of R3 and C1_interstage.

Design centering usually takes care of this optimum adjustment automatically. But now, watch the Yield histogram of capacitor C1 of the output matching network. This capacitor is very sensitive and it drops the yield down in both directions.

This is a Red X component and it is dangerous and causing the poor yield. Therefore, just as the DOE determined that the output matching network is very sensitive and must be redesigned, Yield Sensitivity Histograms also found this out and picked up the element that is causing this problem.

Therefore, the Output matching network must be redesigned with a better and less sensitive topology.

Final Improved Design

After having designed a new and less sensitive output matching network, we ran Yield analysis, Yield sensitivity histograms, DOE, and Design centering to the new design and we got a robust design that has higher than 95% yield.

The failed trails were due to the few FET samples that are outliers and have low gain and higher noise figure.

NEW! An improved version of the example is available here: Design for Manufacturing with ADS.

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