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Advanced Design System 2008 -
100% Productivity Improvements

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ADS 2008 - 100% Productivity Improvements

Advanced Design System (ADS) 2008 delivers a multitude of new productivity improvements to help you throughout your entire design flow.

The table below shows just a few of the productivity improvements that you can expect from
ADS 2008.

If you are ready to get started using ADS 2008,
please use the ADS 2008 Demo Software Request

Localized Versions

  Japan

Click on an icon for more detail:

Sample
Design Task		 ADS 2006A ADS 2008 Productivity
Improvements
Zoom in schematic or layout
  1. Select Zoom command
  2. Select area to zoom
One step:
Scroll mouse wheel to zoom in or out
 100%
Pan across schematic or layout
  1. Select horizontal and vertical window scroll bar and drag across
  2. Select vertical window scroll bar and drag across
One step:
Click and hold right mouse button then drag OR press keyboard arrow keys
 100%
Copy and re-name/re-version top-level and dependent designs Individually re-name top-level and dependent designs
One step:
Copy design using new Project View
100%+
Insert subnetwork
  1. Open Library Browser
  2. Select subnetwork
  3. Place subnetwork
One step:
Drag subnetwork into Schematic or Layout from new Project View
 200%
Transient simulation of 11,000 nodes† 310 seconds 8 seconds 3800%
View multiple layers all at once Select one layer at a time to view
View all layers at once using new layer transparency
 100%+
Insert trace and vias across 2 layers
  1. Draw trace on layer 1
  2. Select via component
  3. Insert via
  4. Select layer 2
  5. Insert trace
 Two steps:
1. Draw trace on layer 1
2. Draw trace on layer 2 - via is automatically inserted
150%
Insert bondwire
  1. Create schematic
  2. Insert Bondwire component
  3. Insert bond wire shape component
One step:
Insert new JEDEC bondwire directly onto layout
 200%
Momentum simulation with ~10,000 unknowns 23 minutes using single-core computer 9 minutes, 59 seconds using quad-core computer†† 130%
Identify Design Rule errors
  1. Browse disk directories and select rules file
  2. Run Design Rule Check (DRC)
  3. Browse errors one at a time by clicking Next multiple times until desired error is displayed
 Two steps:
1. Rules files are auto-loaded into project; Run Design Rule Check (DRC)
2.All errors are displayed - select error and it is auto- zoomed in the layout
100%+
Access any help document 3+ mouse clicks
One mouse click from ANY page
 200%+
Find power at a circuit node
  1. Insert Current Probe at node
  2. Write Data Display (DDS) expression for DC power
  3. Write another, complex DDS expression for AC power
  4. Display expression results
 Two steps:
1. Place Power Probe at node
2.Directly (no complex expressions are required) display DC and AC results
200%
Find S-Parameters in each direction between every subnetwork in a 3-stage design 1. through 4.
 Create individual S-parameter Test Bench for each combination of subnetworks
5.Display and interpret results to find desired S-parameters.
Two steps:
1. Create a single Test Bench, inserting the SP_Probe between each subnetwork
2.Accurate results in each direction are automatically available for display.
300% or more
† Representative single example; average transient speed-up for circuits > 10,000 nodes is 6X
†† Using new multi-threaded matrix load

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