Agilent EEsof EDA Advanced RFIC Seminar 2004

Advanced RFIC Design Seminar 2004 Europe, 16 - 26 March 2004 United States and Canada, 13 - 30 April 2004
	The Agilent Advanced RFIC Design Seminar is being given in seven cities in Europe, 16 - 26 March 2004, and in twelve cities in the United States and Canada, 13 April to 30 April 2004. This page offers links to more information about the key products and features discussed in the seminar, abstracts of each paper, and links to the complete texts. Key Products and Features Abstracts and Links

Key Products and Features

• RF Design Environment
• RF Design Environment 2003C: Wireless Test Benches
• RF Design Environment 2003C: Momentum
• RF Design Environment 2003C: Verilog-A Compiler
• Agilent Ptolemy Simulator

Abstracts and Links

WLAN-OFDM Transceiver Design and Verification: An Integrated Methodology for System and Circuit Simulations. Presented by Agilent Technologies.

This first paper describes partitioned simulation of a WLAN transceiver and system-level optimization of EVM and BER specifications. In addition, it describes how the specifications are then turned into first-step, realizable RFIC designs in the circuit designer's native environment. The second part of this paper discusses circuit simulation and analysis of the design.

As the design work progresses, more realistic system-level test benches are available for use with the evolving circuit design for concurrent verification of system-level specifications. The last part of this presentation focuses on how RFIC designers can access the system test benches from within the Cadence framework to verify the behavior of circuit designs at the system level. The final designs that are produced by this methodology have a much higher chance of first-pass success, in less time and requiring fewer resources.

• WLAM-OFDM Transceiver Design and Verification   (PDF, 3.4 MB)

Accurate Modeling of Spiral Inductors on Silicon using Advanced EM Simulation. Presented by Agilent Technologies.

Traditionally, critical passive elements such as spiral inductors were modeled using simple RLC networks. However, due to the resistive loss in the metalization of the spiral coils, the resistivity of the silicon substrate, and the capacitive coupling effects with the substrate, inductors on silicon behave quite differently than ideal inductive components. With the RFDE Momentum EM simulator, integrated into the Cadence Virtuoso Custom IC Design Platform, accurate characterization of the electrical behavior of these spiral inductors is possible. The RFDE Momentum EM simulator models the critical physical parasitics, allowing RFIC designers to create spirals with maximum quality factor (Q) at the desired operating frequency, with the desired inductance value and available substrate "floor space."

• Accurate Modeling of Spiral Inductors on Silicon   (PDF, 1.3 MB)

A 1.7-GHz VCO implemented in austriamicrosystems' 0.35-µm HBT BiCMOS Process. Presented by austriamicrosystems.

Through a 1.7-GHz VCO design example, this presentation shows how RFDE helped austriamicrosystems to see a strange measured phase-noise behavior in simulation that was not detected with the initial simulator. This presentation will also give an overview of austriamicrosystems as a company and introduce in more detail the Full Service Foundry Business Unit, its portfolio, and a detailed view of the 0.35-µm HBT BiCMOS.

• 1.7-GHz VCO implemented in austriamicrosystems' 0.35-µm HBT BiCMOS Process   (PDF, 2.01 MB)

"Meet-in-the-Middle" - Leveraging the speed of the top-down design methodology combined with the silicon accuracy of bottom-up design capabilities. Presented by Cadence Design Systems.

The advanced custom design (ACD) methodology relies on a "meet-in-the-middle" approach as the most pragmatic method to achieving predictability in complex designs. This presentation uses a WLAN 802.11a reference design to show how to re-use wireless library models and test benches from the system environment within AMS Designer, Cadence's multi-language mixed-signal environment, to validate the full-chip specification. Implementation steps are described, starting from the system and behavioral level and focusing on the bottom-up design process, including model calibration, resulting in faster models and reduced simulation times for large ICs.

• "Meet-in-the-Middle" - Leveraging the speed of the top-down design methodology combined with the silicon accuracy of bottom-up design capabilities   (PDF, 1.7 MB)