Examples > RF Board > Automatic Gain Control Loop
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Power Amplifier with IS-95 CDMA Source InputPower Amplifier using Cartesian Feedback

Simulation of An Automatic Gain Control Loop

Location: /examples/RF_Board/AGC_wDownConv_prj

Objective

This example shows simulations of a basic automatic gain control (AGC) loop. The AGC loop is based on an ideal voltage controlled amplifier, either an AM demodulator or a simple diode can be used at the amplifier output, and its output is compared to a reference voltage. Idealized op-amp is used as the integrator and to produce the control voltage. AGC with a Quadrature Phase-Shift Keyed (QPSK) source is also tested.

Setup

  1. "B_VCAtest" shows the simulation of a voltage-controlled amplifier, which is the basic element for the following AGC loop.

  2. "C_AGCtest" shows the transient response of a simple AGC loop where the reference voltage at the integrator input is stepped. "D_PinChange" is another similar test with the input signal power stepped instead.

  3. "F_wDetector" simulates the AGC loop with the detector replacing the AM demodulator, with stepped reference voltage. "Detector" shows the simple diode. "E_DetectorTest" simulates its output voltage versus input power.

  4. "G_wDownConvOL" and "H_wDownConv" add a stage of downconversion (an ideal mixer) between the amplifier and detector for open and closed loop respectively. "I_wDownConvOL" and "J_wDownConvOpAmp0" use an AM instead of the diode detector.

  5. "L_wQPSKsource" uses an QPSK source. " M_wQPSKsrc_wDet" is similar and uses the diode detector. "QPSKsourceTest" simulates the QPSK signal driving a resistor.

Gain control loop schematic

Analysis

Amplifier IF output power, and stepped input power

Figure 1: Amplifier, IF output power, and stepped input power. The amplifier and IF output powers change in response to variations in input power due to the QPSK modulation, but the loop forces them back to their target levels.

IF, detector, and integrator output voltage

Figure 2: IF, detector, and integrator output voltage. The integrator output voltage steps down in response to increases in the input power, to force the IF output voltage to be constant.

Notes

  • Note that in "K_FreqResp.dsn" the switch in the integrator feedback path has been replaced by a large resistor. Otherwise the feedback will be shorted out (for harmonic balance simulations.)